Opened 5 years ago

Closed 5 years ago

Last modified 5 years ago

#634 closed defect (invalid)

intra_mip_flag signalling condition issue in VVC D7 vA

Reported by: rickxu Owned by:
Priority: minor Milestone:
Component: spec Version:
Keywords: Cc: ksuehring, bbross, XiangLi, fbossen, jvet@…


In VVC draft 7 vA, the intra_mip_flag is signaled without checking the CU size. In the Geneva meeting note, it was adopted that "MIP is allowed up to 64x64 regardless of the maximum transform size.". So the signaling condition should be changed as below.

if( sps_mip_enabled_flag && cbWidth <= 64 && cbHeight <= 64 )

intra_mip_flag[ x0 ][ y0 ]

Change history (2)

comment:1 Changed 5 years ago by bbross

  • Resolution set to invalid
  • Status changed from new to closed

Dear Rick,

Thanks for reporting. The draft text is what we adopted at the last meeting.
When the notes say "MIP is allowed up to 64x64 regardless of the maximum transform size." it refers to the mode signalling.
This means that for > 64x64 CUs you can still signal MIP, but the TU sizes are smaller depending on max trafo size.
Please note that the actual prediction size is the TU size which is always <=64x64.
This fully aligned MIP with regular intra prediction in this regard.
Hope that clarifies the adoption.

BR, Ben

comment:2 Changed 5 years ago by zhou

I am in the same understanding as Rick that the adoption is to enable the MIP up to 64x64 CU size when the maximum TU size is 32x32. Both JVET-P0198 and JVET-P0352 seem to say so. Any benefit by enabling the MIP for 64x128/128x64/128x128 CU sizes, those CUs contain multiple VDPUs.

Best Regards,


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