Mismatch with spec on slice_address coding

[forayr]

The issue happens when single_tile_in_pic_flag = 1 and signalled_slice_id_flag = 0.

In this case, according to the specification:

• single_brick_per_slice_flag is inferred to 1
• num_slices_in_pic_minus1 is inferred to NumBricksInPic − 1 = 0
• rect_slice_flag is inferred to 1
• signalled_slice_id_length_minus1 is inferred to Ceil( Log2( num_slices_in_pic_minus1 + 1 ) ) - 1 = -1

Therefore slice_address is coded on signalled_slice_id_length_minus1 + 1 bit = 0 bit.

In the VTM, slice_address is coded on 1 bit:

int bitsSliceAddress = 1;
if (!pps->getRectSliceFlag())
{
  while (pps->getNumTilesInPic() > (1 << bitsSliceAddress))  //TODO: use the correct one
  {
    bitsSliceAddress++;
  }
}
else
{
  if (pps->getSignalledSliceIdFlag())
  {
    bitsSliceAddress = pps->getSignalledSliceIdLengthMinus1() + 1;
  }
  else
  {
    while ((pps->getNumSlicesInPicMinus1() + 1) > (1 << bitsSliceAddress))
    {
      bitsSliceAddress++;
    }
  }
}

[forayr]

MR: ​https://vcgit.hhi.fraunhofer.de/jvet/VVCSoftware_VTM/merge_requests/627

[hendry197]

The software is correct. When there is only one slice in the picture, it is treated as rectangular slice. For rectangular slice, the intent is to always have slice_address signalled to support extraction case. Thus, the number of bits for signalling slice_address must be greater than 0.

The problem is with the spec. In inference value for syntax element signalled_slice_id_length_minus1 should be corrected to be: Ceil( Log2( Max(2, num_slices_in_pic_minus1 + 1 ) ) ) − 1, instead of the current inference Ceil( Log2( num_slices_in_pic_minus1 + 1 ) ) − 1

This is spec bug and needs to be fixed as described above.

[bbross]

Will be fixed in vD