Opened 4 weeks ago

Closed 3 weeks ago

#695 closed defect (duplicate)

1st PTL cannot refer to 0th PTL's profile/tier/general constraints when pt_present_flag[1] is equal to 0

Reported by: tsukuba.takeshi Owned by:
Priority: minor Milestone:
Component: spec Version: VVC D7 vE
Keywords: Cc: ksuehring, bbross, XiangLi, fbossen, jvet@…

Description

In JVET-P2001vC,
when pt_present_flag[ i ] is equal to 0,
i-th PTL's profile/tier/general constraints information can be inferred from (i-1)-th PTL's as below.

"""the profile, tier, and general constraints information for the i-th profile_tier_level( ) syntax structure in the VPS are inferred to be the same as that for the ( i − 1 )-th profile_tier_level( ) syntax structure in the VPS.
"""

However, 1st PTL cannot refer to 0-th PTL's profile/tier/general constraints information when pt_present_flag[1] is equal to 0, because pt_present_flag[0] of 0-th PTL is inferred to be equal to 0, which means 0-th PTL has no profile/tier/general constraints information.

Suggested solution as below:
The value of pt_present_flag[ 0 ] is inferred to be equal to 01.

Change history (4)

comment:1 Changed 4 weeks ago by tsukuba.takeshi

Ticket #696 has been marked as a duplicate of this ticket.

comment:2 Changed 4 weeks ago by bbross

  • Version changed from VVC D7 vC to VVC D7 vD

comment:3 Changed 4 weeks ago by bbross

  • Version changed from VVC D7 vD to VVC D7 vE

comment:4 Changed 3 weeks ago by vdrugeon

  • Resolution set to duplicate
  • Status changed from new to closed

Closed as duplicate of #672.

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